3
학생이 쓴 원문
강사 첨삭
Whew, the final answer :)
Therefore, I checked performance of jitter and skew of each clock.
>>Therefore, I checked the performance of jitter and skew of each clock.
I measured each signal with an oscilloscope.
>>CORRECT!
I was able to analyze in more detail by clock signal.
>> I was able to analyze each detail by clock signal.
And I implemented clock calibration logic.
>>CORRECT!
The calibration logic creates the same start sink for a 16-channel clock.
>>CORRECT!
At this time, I tried using the C language because I needed to modify the source of software.
>>CORRECT!
And I can use two languages by converting the code from verilog to VHDL.
>>CORRECT!
I think each language has its pros and cons.
>>CORRECT!
I think Verilog is flexible, but I think it makes VHDL accurate.
>>CORRECT!
I set the pin position of the FPGA for signal performance.
>>CORRECT!
The third company is Hancom UniMax.
>>The third company I worked for was Hancom UniMax.
This company designs interface box in aircraft and helicopter.
>>CORRECT!
I was responsible for circuit design, logic design and avionics certification.
>>CORRECT!
Among them, I focused on the work of avionics certification.
>>CORRECT!
As a matter of fact, There almost aren’t that information in korea because there isn’t case of obtain this certification in Kore
>>As a matter of fact, there almost no available information in Korea, because there wasn\'t a case to obtain this certification here.
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